An optimized architecture for modulo (2n − 2p + 1) multipliers
نویسندگان
چکیده
منابع مشابه
Efficient modulo 2n+1 tree multipliers for diminished-1 operands
In this work we propose a new method for designing modulo 2"+I multipliers for diminished-I operands. Our multipliers compared to the already known tree architecture offer enhanced operation speed for the majority of n values, with similar area complexities. They also have very regular structure, and can be pipelined at the full-adder level.
متن کاملHigh-Speed and High-efficient Modulo (2n-3) Multipliers
In this paper, an algorithm for designing efficient modulo 2n-3 multipliers is proposed. With this algorithm, we can design the fastest among all known modulo 2n-3 multipliers by applying some simple correction terms. Implemented using 90nm CMOS process technology, the proposed modulo 2n-3 multiplier can improve the current state of the art by 3.9% on the average in terms of area and 10.536.4% ...
متن کاملImproved Modulo (2n+1) Multiplier for IDEA
International Data Encryption Algorithm (IDEA) is one of the most popular cryptography algorithms in date since the characteristic of IDEA is suitable for hardware implementation. This study presents an efficient hardware structure for the modulo (2 + 1) multiplier, which is the most time and space consuming operation in IDEA. The proposed modulo multiplier saves more time and area cost than pr...
متن کاملDiminished-1 Modulo 2n + 1 Squarer Design
Squarers modulo M are useful design blocks for digital signal processors that internally use a residue number system and for implementing the exponentiators required in cryptographic algorithms. In these applications, some of the most commonly used moduli are those of the form 2+1. To avoid using (n+1)-bit circuits, the diminished-1 number system can be effectively used in modulo 2+1 arithmetic...
متن کاملImproved Modulo 2n +1 Adder Design
Efficient modulo 2+1 adders are important for several applications including residue number system, digital signal processors and cryptography algorithms. In this paper we present a novel modulo 2+1 addition algorithm for a recently represented number system. The proposed approach is introduced for the reduction of the power dissipated. In a conventional modulo 2+1 adder, all operands have (n+1...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2015
ISSN: 1349-2543
DOI: 10.1587/elex.11.20141054